1. Field of the Invention
This application is based upon and claims the benefit of the priority of Japanese patent application No. 2012-133091, filed on Jun. 12, 2012, the disclosure of which is incorporated herein in its entirety by reference thereto.
This invention relates to a semiconductor device and, more particularly, to a semiconductor device including a through-substrate via.
2. Description of Related Art
Recently, the tendency towards a small size and higher functionality is becoming more apparent in the field of electronic equipment, such as mobile phones or smartphones. For this reason, in a semiconductor device used for such electronic equipment, attempts are ongoing to develop the technology in which a plurality of semiconductor chips are stacked together and the resulting stack product is loaded in a single package.
FIG. 46 shows a cross-sectional view of an example semiconductor device having a plurality of semiconductor chips 12 to 15 stacked together. More specifically, FIG. 46 shows that a plurality of semiconductor chips are stacked on an interfacing chip 11. In such semiconductor chip, the power from a power supply is delivered, in a majority of cases, to each semiconductor chip using a plurality of through-substrate vias (TSVs) 10 penetrating through substrates of the semiconductor chips.
In JP Patent Kokai Publication No. JP2005-210106A (Patent Literature 1), there is shown a semiconductor device in which a through-silicon via constituting an outside-chip signal line is placed adjacent to a through-silicon via constituting a power supply line and a through-silicon via constituting a ground line to reduce the power supply noise.